1. Field of the Invention
The present invention relates to a semiconductor device provided with an element isolation structure.
2. Description of the Background Art
Recently, it is becoming increasingly difficult to improve the driving capability of a MOS transistor formed in a silicon substrate, which is the most important for achieving high operating speed of a CMOS device. As a technique for overcoming this, there has been proposed a method for forming a MOS transistor by utilizing heterojunction to be formed by silicon (Si) and silicon germanium (SiGe).
Based on the document of Kern (Kim) Rim et al., “Fabrication and Analysis of Deep Submicron Strained-Si N-MOSFET's,” IEEE Transactions on Electron Devices, 2000, Vol. 47, No. 7, pp. 1406–1415 (hereinafter referred to as a “document I”), a silicon germanium layer (hereinafter referred to as a “SiGe layer”) after being subjected to lattice relaxation is formed on a silicon substrate, and a silicon layer (hereinafter referred to as a “Si layer”) is formed on the SiGe layer while subjecting it to lattice matching. As a result, the Si layer has tensile strain. This Si layer having tensile strain is hereinafter referred to as a “strained Si layer”. A MOS transistor that utilizes the strained Si layer as a channel (hereinafter referred to as a “strained Si channel MOS transistor”) has higher electron mobility and hole mobility in an inversion layer than a MOS transistor that utilizes a strain-free Si layer as a channel. Therefore, employment of the strained Si channel MOS transistor as a MOS transistor enables to improve the driving capability of the MOS transistor and the operating speed of a CMOS device.
Additionally, the document of K. Ismail, “Si/SiGe High-Speed Field-Effect Transistors,” International Electron Devices Meeting Technical Digest, 1995, pp. 509–512 (hereinafter referred to as a “document II”), proposes a CMOS device that has a modulation dope type n-channel MOS transistor and a p-channel MOS transistor. In the n-channel MOS transistor, an intrinsic strained Si layer into which no impurity is introduced is formed on a SiGe layer into which n-type impurity is introduced, and the strained Si layer is used as a channel. In the p-channel MOS transistor, a strain Si layer free from impurity is formed on a SiGe layer into which no impurity is introduced, and the SiGe layer is used as a channel.
In the CMOS device proposed in the document II, no impurity is introduced into the channel in both of the n-channel MOS transistor and the p-channel MOS transistor. Further, the SiGe layer can obtain higher hole mobility than the strained Si layer. Accordingly, the CMOS device of the document II can improve its operating speed than the CMOS device in which both of the n-channel MOS transistor and the p-channel MOS transistor use the strained Si layer as a channel layer.
Also, a CMOS device utilizing superlattice formed by Si and SiGe as a channel is proposed in the document of J. Alieu et al., “Multiple SiGe well: a new channel architecture for improving both NMOS and PMOS performances,” Symp. VLSI Tech. Digest, 2000, p. 130, 131 (hereinafter referred to as a “document III”).
Thus, the currently proposed CMOS devices utilizing heterojunction for channel employ a compound semiconductor layer such as a SiGe layer or a silicon germanium carbon layer (hereinafter referred to as a “SiGeC layer”). The document of D. K. Nayak et al., “Interface properties of thin oxides grown on strained GexSi1-x layer,” J. Appl. Phys., 1994, Vol. 76, No. 2, pp. 982–988 (hereinafter referred to as a “document IV”), describes the phenomenon that occurs during thermal oxidization of a SiGe layer. Further, Japanese Patent Application Laid-Open No. 11-233610 discloses a technique related to an element isolation structure for separating between semiconductor elements.
In the document IV, there is reported the phenomenon that if a silicon oxide film is formed by thermally oxidizing a SiGe layer, germanium is discharged from the silicon oxide film, and germanium segregates in the interface between the SiGe layer and the silicon oxide film, thereby increasing the interface state density in the interface and the fixed charge in the silicon oxide film.
On the other hand, in trench isolation structure that is dominant of element isolation structure in current semiconductor devices, after forming a trench in a silicon substrate, the inner surface of the exposed silicon substrate is thermally oxidized to form a thermal oxide film on the surface of the trench, and the trench is then filled with an insulating film.
If the trench is filled with the insulating film, without thermally oxidizing the surface of the trench, the interface state density between the insulating film and the silicon substrate is increased. Therefore, in order to suppress this increase to reduce the leakage current of a semiconductor element, the thermal oxide film is formed on the surface of the trench.
In the case where trench isolation structure is employed in a semiconductor device utilizing the above-mentioned heterojunction, an upper-layer strained Si layer has a small film thickness, so that the SiGe layer and the SiGeC layer are exposed by a trench of the trench isolation structure. Therefore, the exposed SiGe layer and the SiGeC layer are thermally oxidized. In the interface between a compound semiconductor layer containing germanium such as the SiGe layer, and the thermal oxide film of the trench isolation structure, the germanium segregates thereby to increase the interface state density in that interface, and increase the fixed charge in the thermal oxide film. As a result, the element isolation characteristic in the semiconductor device might be lowered.